In certain bus systems used to interface a host computer with a number of peripheral devices or units, signal degradation may occur, particularly with respect to certain control signals transmitted between the host unit and the peripheral units each of which signals is often transmitted on its own dedicated control signal bus. Such signal degradation tends to occur during transmission on such buses because of multiple signal reflections due to impedance mis-matches which occur on the bus due to the variations in the input capacitances from peripheral unit to peripheral unit present on the bus. Such effects are particularly noticeable when the bus is relatively heavily loaded, i.e., there are a relatively large number of peripheral units which act to produce an excessive load on the bus. Further, signal degradation is further aggravated because the signal rise times at the host unit and at the peripheral units are often essentially incompatible.
For small computer systems, for example, the American National Standards Institute (ANSI) issues specifications requiring certain standardized operating characteristics for Small Computer System Interfaces (SCSI), i.e., small computer bus systems. Under current industry bus specifications imposed on such bus interfaces, for example, relatively low maximum current carrying or current sink capabilities from devices driving a bus are permitted. Further, earlier specifications imposed no limits on the input capacitances of the peripheral devices used and, although more recent specifications did impose a maximum permissible input capacitance, the limit was set at a relatively high level so that peripheral device manufacturers produce units which still have relatively high input capacitances which differ from product to product. Such relatively high and different input capacitances tend to produce signal degradations due to signal reflections, the severity of the reflections effects depending on both the number and the locations of the devices on the bus.
Further, such specifications require that the total length of the bus and cabling to the peripheral devices be limited to a maximum limit. Under such conditions reasonably reliable bus transmission performance can be expected only if the peripheral devices on the bus are fairly widely spaced apart along the bus.
However, in many applications it is desired to reduce such spacing as much as possible so that a relatively large number of peripheral devices can be used while still maintaining the total bus and cable lengths below the imposed limit thereon. A reduction in spacing may also be desired even with relatively fewer peripheral units in order to provide a desired physical packaging configuration of the units in the overall computer system. Such reduction in spacing, however, tends to aggravate the signal degradation.
Most suggestions for preventing signal degradation under such conditions have involved attempts to provide specially designed impedance terminations at either or both ends of an interface bus system in an effort to reduce the effect of undesired reflections along the bus and to provide an effective overall impedance match in the light of the driver current sink constraint and the lack of any severe constraint on the maximum permissible peripheral unit capacitances in the system. Other suggestions have included a reduction in the normal impedance characteristics of the peripheral cables used to interconnect the peripheral units to the bus and/or of the internal ribbon cables used in the units themselves. Still another suggestion has been to use lossy resistive elements (e.g., ferrite beads) between the bus and a target peripheral unit so as to adjust the input impedance presented to the bus by the unit in order to reduce the loading effects of the unit on the bus.
None of such approaches have proved beneficial in avoiding signal degradation, particularly in avoiding the "notch" effect which is often produced in the control signal being transmitted along the bus and which has a detrimental effect on computer operation, as discussed in more detail below.
It is desired, therefore, to provide an interface system in which peripheral units having a relatively wide variety of relatively high input capacitances can be accommodated, in which the spacings between peripheral units can be made relatively short, if desired, and in which such units can be placed arbitrarily at any position, or "slot", on the bus while minimizing signal degradations. It is further desirable that the signal rise times be appropriately controlled so that, when the rise times among peripheral units and the host are essentially incompatible, the introduction of further signal degradation can be avoided. Such an improved bus interface system should be designed to operate reliably within the industry bus characteristic and bus/cable length standards imposed on such systems.